// // FPGA PACMAN Z80 interface for Basaro's T80 // // Version : beta2 // // Copyright(c) 2002,2003 Tatsuyuki Satoh , All rights reserved // // Important ! // // This program is freeware for non-commercial use. // An author does no guarantee about this program. // You can use this under your own risk. // // // // Additional circuit. // // 1.Clock Synchronizer (use RESET_N raize timming) // 2.Wait Controller // // module Z80IP( A, DIN, DOUT, BUSWO, RESET_N, INT_N, NMI_N, WAIT_N, M1_N, MREQ_N, IORQ_N, RD_N, WR_N, RFSH_N, HALT_N, CLK2X,CLK); // I/O assign output [15:0] A; input [7:0] DIN; output [7:0] DOUT; input RESET_N,INT_N,NMI_N,WAIT_N,CLK2X,CLK; output M1_N,MREQ_N,IORQ_N,RD_N,WR_N,RFSH_N,HALT_N,BUSWO; // // CLK syncronizer // reg reset_sync = 1'b0; always @(negedge CLK2X) begin if(~CLK) reset_sync <= RESET_N; end // // TW cycle detector // reg before_idle,TW_in,TW; reg clk_disable; wire access_cycle = (MREQ_N & IORQ_N); always @(posedge CLK or negedge access_cycle) begin if(~access_cycle) begin before_idle <= 1'b0; TW_in <= 1'b0; end else begin before_idle <= ~access_cycle; TW_in <= before_idle & access_cycle; end end // // TW wait cycle generator // always @(negedge CLK or negedge access_cycle) begin if(~access_cycle) begin TW <= 1'b0; end else begin if( TW_in | TW) TW <= ~WAIT_N; end end // // skip CLK2X in WaitCycle // wire ZCLK = CLK2X | TW; // Z80IP interface Z80TOP z80core ( .CLK(ZCLK), .RESET_N(reset_sync), .INT_N(INT_N), .NMI_N(NMI_N), .A(A), .D(DOUT), .DIN(DIN), .M1_N(M1_N), .MREQ_N(MREQ_N), .IORQ_N(IORQ_N), .RD_N(RD_N), .WR_N(WR_N), .BUSWO(BUSWO), .RFSH_N(RFSH_N), .HALT_N(HALT_N) ); endmodule