----------------------------------------------------------------------------- FPGA TilePilot Clone version 0.91 documentation. 2004.8.19 Tatsuyuki Satoh ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- FPGA TimePilot specification. ----------------------------------------------------------------------------- 1.Game Playable full function with sound on XC2S300E or larger (*1)(*2). 2.Game Playable without sound on XC2S200. 3.Circuit Clone over 90% and some useful additional circuit. 4.Included customized Daniel Wallner's T80 open-source CPU-IP. 5.The code is written with 100% verilog-HDL without T80. 6.few parts are necessary outside the FPGA. -programmed PROM or FlashROM(150ns access time). -18.432MHz clock source -17xregister for RGB/VGA output. -1xRegister and 1xCapacity for analog sound output. -configration ROM or ISP configration circuit. -5xPush switch or PSX PAD for controller 7.optional 31KHz standard VGA timing output by the built-in up-scan converter. 8.An analog sound output with one bit SignaDelta-DAC. 9.Only one EEPROM (or EPROM) necessary. -main CPU , sub CPU , TilePattern , ObjPattern are sharing one! -TileCLUT , ObjCLUT , Palette ROM are preloaded by autoload circuit. 10.In the future plan, -HDTV(Y,Pb,Pr) video encoder -PS2 Keyboard HID -SPDI/F digital-sound encoder -DOS/V GAME port HID etc. *1:I tested on XCM-001-400(XC3S400 pcb) + some circuit. *2:K.Degawa tested on XC2S300E and EP1C12Q240C8. ----------------------------------------------------------------------------- changes 0.90 to 0.91 ----------------------------------------------------------------------------- 1.main target board changed to XC3S400 from XC2S200. 2.cahnge external ROM access timming 6slice@1.5MHz to 4slice@1.5MHz. An access time was changed to 150ns. 3.some bugfix and tested for Altera Quartus 4.0sp1 By K.Dwgawa. *The project/source file of cyclone are not included in this archive. 4.remove xilinx dependent primitive in VGA upscan converter. 5.added psx-pad HID support. used K.Degawa's psx-pad access ip. 6. bugfix flip screen & cooktail 2player controll ----------------------------------------------------------------------------- controll switch assign ----------------------------------------------------------------------------- 1.direct switch HID UP 1P/2P : HID0 Active low RIGHT 1P/2P : HID1 Active low LEFT 1P/2P : HID2 Active low DOWN 1P/2P : HID3 Active low FIRE 1P/2P : HID4 Active low START 1P : LEFT (+ RIGHT off) START 2P : RIGHT (+ LEFT off) COIN1 : LEFT + RIGHT + UP (+ DOWN off) COIN2 : N.A. RESET : LEFT + RIGHT + UP + DOWN 2.PSX PAD HID UP 1P/2P : arrow Up RIGHT 1P/2P : arrow Right LEFT 1P/2P : arrow Left DOWN 1P/2P : Arrow Down FIRE 1P/2P : Circle START 1P : START START 2P : Square COIN1 : SELECT COIN2 : N.A. RESET : L1 + R1 + SELECT + START ----------------------------------------------------------------------------- external EEPROM(timeplt.bin) memory map ----------------------------------------------------------------------------- +---------+-----+-----------------------------------------+ |ROM Area |Parts| Contents | +---------+-----+-----------------------------------------+ |0000-1fff| H2? |MainCPU ROM 0000-1fff | |2000-3fff| H3? |MainCPU ROM 2000-3fff | |4000-5fff| H4? |MainCPU ROM 4000-5fff | |6000-7fff| H5? |MainCPU ROM 6000-7ffff(no use) | +---------+-----+-----------------------------------------+ |6000-60ff| E12 |Tilemap ColorLookUpTable ROM (*1)(*2) | |6100-61ff| E9 |Object ColorLookUpTable ROM (*1)(*2) | |6200-621f| B4 |Palette ROM H (*1)(*2) | |6220-623f| B5 |Palette ROM L (*1)(*2) | |6240-625f|(B4) |YPrPb PaletteTable for HDTV (*1)(*2)(*3)| |6260-627f|(B5) |YPrPb PaletteTable for HDTV (*1)(*2)(*3)| +---------+-----+-----------------------------------------+ |8000-9fff| C10?|Object Pattern ROM1 | |a000-bfff| C11?|Object Pattern ROM2 | +---------+-----+-----------------------------------------+ |c000-dfff| F11 |Tilemap Pattern ROM | +---------+-----+-----------------------------------------+ |e000-efff| A7 |SoundCPU ROM 0000-0fff | |f000-ffff|(A8) |not used | +---------+-----+-----------------------------------------+ *1: These overlap with MainCPU. *2: load to internal memory after reset. *3: reserved for future. ----------------------------------------------------------------------------- DIP SWITCH setting ----------------------------------------------------------------------------- define macros in 'switch.vh' ----------------------------------------------------------------------------- How To Build and play game ----------------------------------------------------------------------------- ---------------------------------------- 1.build TimePilot ROM data 1)copy there file to work directry. +-------------+--------------------------+------+ |make_rom.bat | batch file | ---- | |dmy1dc0 . | dummy PAD file | 1dc0h| +-------------+--------------------------+------+ 2)drop TimePilot ROM file to work directry, +-------------+--------------------------+------+ |filename | Contents | size | +-------------+--------------------------+------+ |tp1 . | Main CPU code 0000-1fff | 2000h| |tp2 . | Main CPU code 2000-3fff | 2000h| |tp3 . | Main CPU code 4000-5fff | 2000h| |timeplt .e12 | Tilemap ColorLookUpTable | 0100h| |timeplt .e9 | Object ColorLookUpTable | 0100h| |timeplt .b4 | Palette High word | 0020h| |timeplt .b5 | Palette Low word | 0020h| |tp4 . | Object Pattern ROM1 | 2000h| |tp5 . | Object Pattern ROM2 | 2000h| |tp6 . | Tilemap Pattern ROM | 2000h| |tp7 . | SubCPU code | 1000h| +-------------+--------------------------+------+ 3)execute make_rom.bat on Command Prompt 4)check file tileplt.bin size are 61440. ---------------------------------------- 2.Burn timeplt.bin to PROM or FlashROM with your writer. ---------------------------------------- 3.Build T80 netlist file. 1.open project 't80as_nb_nn.npl' ,choise your FPGA device and execute Synthesize-XST. 2.open project 't80as_nb_ni_np_nm.npl',choise your FPGA device and execute Synthesize-XST. 3.copy all *.ngc file to timepilot *.npl directry. ---------------------------------------- 4.Build timeplt bitstream file 1)Put all project files and t80 ngc files on the work directory. 2)open project 'ftp_xc3s.npl' with Xilinx Webpack 6.2.03i. 3)choose your FPGA device Spartan3, SpartanII or SpartanIIE . and change ucf file to your pin layout. 4)customize additional circuit , change define in 'switch.vh' If source tree changed by the change of switch.vh, delete "ftp_xc3s.dhp" after close project and reopen project for refresh source tree. 5)Adjust Options for your environment. , JTAG/CCLK , etc. 6)Choice 'fpga_tpx' and execute 'Generate Programming File'. 7)Wait until done!. ---------------------------------------- 5.Setup & Play GAME! 1)Make a FPGA-TimePilot board in accordance with the circuit figure. 2)Burn timeplt.bin to ROM and set FPGA-TimePilot board. 3)Connect VGA otuput of FPGA-TimePilot and RGB or VGA monitor. 4)Connect sound output of FPGA-TimePilot and a analog input of audio amp. 5)Mount burned FPGA-TimePilot ROM. 6)FPGA-TimePilot power on. 7)download Configration-file with JTAG programmer. Good Luck! ----------------------------------------------------------------------------- Selectable Switches in 'switch.vh' ----------------------------------------------------------------------------- I/O pin / grobal clock primitive +--------------------+--------------------------------------------+ |`define SPARTAN2_IO | chose the Spartan dependence primitive |*default |`define CYCLONE_IO | chose the Cyclone dependence primitive | | | (by K.Dwgawa) | +--------------------+--------------------------------------------+ PROM address length (MSB bit number) +------------------------+-----------+ |`define ROM_MSB 18 | 4MBit |*default +------------------------+-----------+ PROM area over 64K +------------------------+-----------+ |`define ROM_BANK 3'b000 |00000-0ffff|*default |`define ROM_BANK 3'b001 |10000-1ffff| +------------------------+-----------+ Video Encoder +------------------------------+-----------------+ |`define VENC_MODULE venc_rgb | 15bpp 16KHz RGB |*default |`define VENC_MODULE venc_vga | 15bpp VGA | +------------------------------+-----------------+ |`define VENC_MODULE venc_ntsc | Future | |`define VENC_MODULE venc_hdtv | Future | +------------------------------+-----------------+ Sound Encoder +------------------------------+------------------+ |`define SENC_MODULE senc_dmy | no sound | |`define SENC_MODULE senc_sd | SigmaDelta Analog|*default |`define SENC_MODULE senc_spd | Future | +------------------------------+------------------+ HumanInterfaceDevice (Controller) +------------------------------+---------------------+ |`define HID_MODULE hid_sw | direct switch | |`define HID_MODULE hid_pspd | PSX game PAD |*default |`define HID_MODULE hid_jmem | JTAG debug controll | +------------------------------+---------------------+ SUB CPU (sound) select +----------------------------+---------------------+ |`define SUB_MODULE tp_sub |with sound(XC3S400) |*default |`define SUB_MODULE tp_sub_d |no sound (XC2S200) | +----------------------------+---------------------+ Intermal Memory Module +-----------------------------+-----------------------------+ |`define IMEM_MODULE imem_gen | Generic RAM (*) |*default |`define IMEM_MODULE imem_xc2 | Xilinx SpartanII / IIE | |`define IMEM_MODULE imem_cyc | Altera Cyclone | +-----------------------------+-----------------------------+ (*)It can be used with Spartan3 and Cyclone. Main CPU Z80 module +--------------------------------------+------------------------+ |`define MCPU_MODULE T80as | T80 full spec |*default |`define MCPU_MODULE T80as_nb_ni_np_nm | T80 customized edition | |`define MCPU_MODULE z80_jmem | JTAG test module | |`define MCPU_MODULE z80_dmy | no CPU | +--------------------------------------+------------------------+ Sub CPU Z80 module +--------------------------------------+------------------------+ |`define MCPU_MODULE T80as | T80 full spec |*default |`define MCPU_MODULE T80as_nb_nn | T80 customized edition | |`define MCPU_MODULE z80_jmem | JTAG test module | |`define MCPU_MODULE z80_dmy | no CPU | +--------------------------------------+------------------------+ ----------------------------------------------------------------------------- timeplt source files ----------------------------------------------------------------------------- +-------------+---------------------------------------------------------+ |filename | contents | +-------------+---------------------------------------------------------+ | ftp_xc3s.npl| WebPack 6.2.03i Project file for XC3S400 | +-------------+---------------------------------------------------------+ |cyclone\ | for Cyclone (by K.Degawa) | | fpga_tpx.qpf| QuartusII 4.0sp1 project file | | fpga_tpx.qsf| QuartusII 4.0sp1 project file | +-------------+---------------------------------------------------------+ |pibout\ |(xilinx pin assign file) | | XCM001.ucf | for XCM-001-400(XC3S400) | | XC2S200.ucf | for my XC2S200 pcb | +-------------+---------------------------------------------------------+ |src\ |(top & common) | | switch.vh | option select swtich | | fpga_tpx.v | top of FPGA design | | extmem.v | external ROM interleave access | | imem_xc2.v | SpartanII/E Internal Memory & preload ROM | | sub_clk.v | Digital PLL sound clock generator | +-------------+---------------------------------------------------------+ |src\tp_main\ |(Main Board) | | tp_main.v | TimePilot Main Board(+I/O) top level | | tp_adec.v | Address Decoder | | tp_clk | Clock Generator | | tp_inp | Input Port | | tp_irq | IRQ Controll | | tp_vid | Video Controller | | tp_vtmg | Video Timming Generator | +-------------+---------------------------------------------------------+ |src\tp_sub\ |(Suound Board) | | tp_sub.v | TimePilot Sound Board top level | | ay8910.v | AY-3-8910 PSG | | mixer.v | sound mixer | | rc_filt.v | sound RC filter (dummy) | | tp_sub_d.v | TimePilot Sound Board dummy | +-------------+---------------------------------------------------------+ |src\t80_ngc\ |(Z80 netlist) | | T80as.v | t80as.ngc interface | | Z80_dmy.v | t80 dummy | +-------------+---------------------------------------------------------+ |src\exp\ | | | hid_cdsw.v | HID Direct Switch Interface | | hid_pspd.v | HID PSX PAD Interface | | psPAD_top.v | Katsumi Degawa's PSX PAD INTERFACE module | | senc_dmy.v | sound encoder dummy | | senc_sd.v | sound encoder Sigma-Delta 1bit DAC | | venc_rgb.v | video encoder 15bpp 15KHz | | venc_vga8.v | video encoder VGA 15bpp | +-------------+---------------------------------------------------------+ |src\debug\ | | | jtagmem.v | jtagmem.ngc interface , JTAG memory control l | hid_jmem.v | HID JTAG debug controll | | z80_jmem.v | Z80 - JTAG debug controll | +-------------+---------------------------------------------------------+ | jtagmem.ngc | JTAG test module netlist (SpartanII) | +-------------+---------------------------------------------------------+ ----------------------------------------------------------------------------- T80 original & customize source files ----------------------------------------------------------------------------- src\t80_src directry +-----------------------+-----------------------------------------+ | filename | contents | +-----------------------+-----------------------------------------+ |T80_src\ | | | T80_Pack.vhd | (T80.0427 original) | | T80.vhd | (T80.0427 original) | | T80a.vhd | (T80.0427 original) | | T80s.vhd | (T80.0427 original) | | T80se.vhd | (T80.0427 original) | | T80_ALU.vhd | (T80.0427 original) | | T80_Mcode.vhd | (T80.0427 original) | | T80_reg.vhd | (T80.0427 original) | | T80_regX.vhd | (T80.0427 original) | +-----------------------+-----------------------------------------+ |T80_src\ | | | T80as.vhd | modified 't80a.vhd' | | T80as_nb.vhd | t80as without BUSRQ | | T80as_nb_ni.vhd | t80as without BUSRQ,INT | | T80as_nb_ni_np.vhd | t80as without BUSRQ,INT,PORT | | T80as_nb_ni_np_nm.vhd | t80as without BUSRQ,INT,PORT,M1 | | T80as_nb_nn.vhd | t80as without BUSRQ,NMI | | T80_nb.vhd | t80 without BUSRQ | | T80_nb_ni.vhd | t80 without BUSRQ,INT | | T80_nb_ni_nm.vhd | t80 without BUSRQ,INT,M1 | | T80_nb_nn.vhd | t80 without BUSRQ,NMI | | T80_RegXM.vhd | minimized T80_regX.vhd | +-----------------------+-----------------------------------------+ | T80as_nb.npl | Project file for ngc build | | T80as_nb_ni.npl | Project file for ngc build | | T80as_nb_ni_np.npl | Project file for ngc build | | T80as_nb_ni_np_nm.npl | Project file for ngc build | | T80as_nb_nn.npl | Project file for ngc build | +-----------------------+-----------------------------------------+ ----------------------------------------------------------------------------- Special Thanks ----------------------------------------------------------------------------- Daniel Wallner -T80 free-ware Z80 module Katsumi Degawa -PSX-PAD module -Cyclone porting ,test and some bugfix HuMANDATA LTD. (osaka,Japan) http://www.hdl.co.jp/home.html -The XCM-001-400 was provided from thre. (http://www.hdl.co.jp/XCM-001/index.html)