----------------------------------------------------------------------------- FPGA PACMAN version ver.0.92 documentation. 2004.9.17 Tatsuyuki Satoh ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- FPGA PACMAN specification. ----------------------------------------------------------------------------- 1.supported devices are XC2S100 or larger FPGA , my main target chip is XC3S400(*1). 2.Game playable full function with sound on XC2S100(*2). 3.use Y.Kuwahara's fz80 , or Guy Hutchison's TV80 to internal Z80 circuit. (Now the fz80 can't execute on AlteraCyclone.) 4.source codes are written with verilogHDL 100%. 5.Only a few parts are necessary outside FPGA. 6.Only one EEPROM (or EPROM) necessary. -CPU and pattern ROM bus are time sharing. -clut,palette,sound wave ROM are copied to FPGA-BSRAM at power up with build-in Z80bootcode. 7.some addin module are included. -31KHz standard VGA timing output by the built-in up scan converter. -SigmaDelta 1bit Sound DAC. -PSX PAD to controller. -OnScreenDisplay 1P/2P lamp and coin counter. 8.In the future plan,many addin module support. -SPDI/F digital-sound (5.1ch DTS?). -PS/2 keyboard. -DOS/V GAME port joystick. -HDTV video encoder. -NTSC video encoder. -H/V video angle re-sampler. -Dynamic ROM data load from configration ROM to SRAM. -Dynamic ROM data load from memory-card. *1: HDL XCM-001-400 board + PROM + 3xDAC + SigmaDeltaDAC. *2: XC2S100 can't mount OSD and PSPAD at the same design. ----------------------------------------------------------------------------- What's change beta2 to 0.92 ----------------------------------------------------------------------------- 1.currentry Z80 core is fz80,and selectable Guy Hutchison's TV80. 2.The big change of the source tree and module name. 3.The implement tool changes to Webpack 6.2.03i from 5.1i. 4.support PSX-PAD HID device and new switch combination. 5.OnScreenDisplay,display the 1P/2P lamp and coin counter. 6.The internal ROM data are dynamic loaded from PROM. 7.Added generic RAM module to internal-memory. 8.The Daniel Wallner's T80 and Basaro's Z80-IP are drop out. 9.NTSC encoder was not maintained. ----------------------------------------------------------------------------- controll switch assign ----------------------------------------------------------------------------- +---------+--------------------+---------------+ |action | direct switch (*1) | PSX PAD | +---------+--------------------+---------------+ |1P UP | HID0 |arrow Up | |1P RIGHT | HID1 |arrow Right | |1P LEFT | HID2 |arrow Left | |1P DOWN | HID3 |arrow Down | |2P UP | HID0 |arrow Up | |2P RIGHT | HID1 |arrow Right | |2P LEFT | HID2 |arrow Left | |2P DOWN | HID3 |arrow Down | |COIN | HID5 + HID0(UP) |SEL | |1P START | HID5 + HID2(LT) |START | |2P START | HID5 + HID1(RT) |Square | |RESET | HID0+HID1+HID2+HID3|L1+R1+SEL+START| +---------+--------------------+---------------+ *1:all HID pins are active low input. ----------------------------------------------------------------------------- external EEPROM(pac.bin) memory map ----------------------------------------------------------------------------- +-----------+----+-----------------------------+ |ROM Address|loc.| contents | +-----------+----+-----------------------------+ |00000-00FFF| 6E | Z80 code (0000-0FFF) | |01000-01FFF| 6F | Z80 code (1000-1FFF) | |02000-02FFF| 6H | Z80 code (2000-2FFF) | |03000-03FFF| 6J | Z80 code (3000-3FFF) | +-----------+----+-----------------------------+ |04C00-04CFF| 1M | SOUND WAVE ROM | |04D00-04DFF| 4A | ColorLookupTable ROM | |04E00-04E1F| 7F | Video Palette ROM | |04E00-04E1F| 7F | HDTV encode table (future) | |04E00-04E1F| 7F | NTSC encode table (future) | +-----------+----+-----------------------------+ |06000-06FFF| 5E | TILE PATTERN DATA | |07000-07FFF| 5F | OBJECT PATTERN DATA | +-----------+----+-----------------------------+ ----------------------------------------------------------------------------- DIP SWITCH setting ----------------------------------------------------------------------------- The setup of the DIP switch is a circuit fixation. DIP switches can be set up in 'switch.v'. ----------------------------------------------------------------------------- How To Build and play game ----------------------------------------------------------------------------- ---------------------------------------- 1.convert and insert PACMAN ROM data 1)drop there files in same directry. make_rom.bat : batch file dmy0c00 : dummy data dmy11e0 : dummy data pacman .6e : Z80 code 0000-0fff (size=0x1000) pacman .6f : Z80 code 1000-1fff (size=0x1000) pacman .6h : Z80 code 2000-2fff (size=0x1000) pacman .6j : Z80 code 3000-3fff (size=0x1000) 82s126 .1m : SOUND WAVE ROM (size=0x100) 82s126 .4a : ColorLookupTable ROM (size=0x100) 82s123 .7f : Video Palette ROM (size=0x20) pacman .5e : TILE PATTERN DATA (size=0x1000) pacman .5f : OBJECT PATTERN DATA (size=0x1000) 2)execute make_rom.bat output files are pacrom .bin: FPGA-PACMAN EEPROM binary data check file size 32768bytes. ---------------------------------------- 2.Burn pacrom.bin to your EEPROM or EPROM ---------------------------------------- 3.Build bitstream file 1)Put all source files on the work directory. 2)Open .npl project file with Xilinx Webpack 6.2.03i 3)Adjust Options for your environment.,JTAG/CCLK,.ucf pin layout,HID device,etc. 4)select design and addon circuit to switch.v 5)Choice 'fpga_pac' and execute 'Generate Programming File'. 6)Wait until done!. ---------------------------------------- 5.Setup & Play GAME! 1)Make a FPGA-PACMAN board in accordance with the circuit figure. 2)Burn pac.bin to EEPROM or EPROM and set FPGA-PACMAN board. 3)Connect VGA otuput of FPGA-PACMAN and standard VGA monitor. 4)Connect sound output of FPGA-PACMAN and a analog input of audio amp. 5)Mount burned FPGA-PACMAN EEPROM. 6)FPGA-PACMAN power on. 7)download Configration-file with JTAG programmer. Enjoy!! ----------------------------------------------------------------------------- source files ----------------------------------------------------------------------------- Xilinx device dependent +-------------+-------------------------------------------+ |filename | contents | +-------------+-------------------------------------------+ |.\ |(Xilinx ISE Project file) | |fpac_xc3.npl | XCM-001-400(XC3S400-pq208) | |fpac_xsp5.npl| XSP-005(XC2S100-tp144) | |fpac_xc2s.npl| XC2S200-pq208 | +-------------+-------------------------------------------+ |ucf\ |(Xilinx pin assign file) | |xcm001.ucf | pin assign for XCM-001-400(XC3S400-pq208) | |xsp005.ucf | pin assign for XSP-005(XC2S100-tq144) | |xc2s200.ucf | pin assign for XC2S200-pq208 | +-------------+-------------------------------------------+ fpga pacman design +-------------+-------------------------------------------+ |filename | contents | +-------------+-------------------------------------------+ |src\ |(fpga pacman top level) | | switch.v | design select & option switch | | fpga_pac.v | top of fpga pacman | | im_gen.v | generic internal memory module | | pac_emem.v | external PROM interleave access | | pac_prom.v | pre-load internal ROM only | | pac_cfr.v | dummy | +-------------+-------------------------------------------+ |src\xilinx |(Xilinx chip dependent file) | |src\pacman\ |(PACMAN main pcb circuit) | | pacman.v | top level | | pac_adec.v | address decoder | | pac_clk.v | clock generator | | pac_inp.v | input ports | | pac_irq.v | IRQ controll | | pac_snd.v | sound generator | | pac_vid.v | video circuit | +-------------+-------------------------------------------+ |src\addin\ |(Additional Circuit) | | senc_sd.v | sound encoder 1bit sigmaDelta | | senc_dmy.v | sound encoder no sound | | venc_rgb.v | video encoder module , 'through' | | venc_vga8.v | video encoder module , 'VGA 8BPP' | | venc_ntsc.v | video encoder module , 'NTSC' | | hid_cdsw.v | HID direct switch interface | | hid_pspd.v | HID PSX-PAD interface | | pac_osd | OnScreenDisplay | +-------------+-------------------------------------------+ |src\ntsc\ |(beta2 NTSC encoder,there are not checked) | | resample.v | 'NTSC' pixel resampler | | rgb_yuv.v | 'NTSC' color space converter | | ntsc_enc.v | 'NTSC' encoder | +-------------+-------------------------------------------+ other auther's IP's +-------------+-------------------------------------------+ |filename | contents | +-------------+-------------------------------------------+ |src\fz80\ |(Y.Kuwahara's Z80 soft core) | | fz80c.v | Z80 Bus Compatible wrapper (My design) | | fz80.v | fz80 soft core | +-------------+-------------------------------------------+ |src\tv80\ |(Guy Hutchison's Z80 soft core) | | tv80c.v | Z80 Bus Compatible wrapper (My design) | | tv80_core.v | TV80 soft core (one fixed) | | tv80_alu.v | TV80 soft core | | tv80_mcode.v| TV80 soft core (one fixed) | | tv80_reg.v | TV80 soft core | +-------------+-------------------------------------------+ |src\pspad\ |(K.Degawa's PSX controller) | | psPAD_top.v | PSX PAD controller | +-------------+-------------------------------------------+ ----------------------------------------------------------------------------- Special Thanks ----------------------------------------------------------------------------- Daniel Wallner -T80 free-ware Z80 module (Do not use now) Katsumi Degawa -PSX-PAD module -Cyclone porting ,test and bugfix HuMANDATA LTD. (osaka,Japan) The XCM-001-400 was provided from thre. XCM-001-400 XSP005 Guy Hutchison - TV80 free-ip Z80 module Y.Kuwahara. - fz80.v pre-release and bugfix. ----------------------------------------------------------------------------- HISTRY ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- What's change beta1 to beta2 ----------------------------------------------------------------------------- 1.All internal Memory component of Xilix dependent was moved to xmemory.v. (For Altera user?) 2.The SoundGenerator was rebuilt to minimize. 3.timing bug about LineRAM was fixed,and timing patch was removed. 4.clock hazard bug in Clock generator was fixed. 5.bug of IRQ vector size was fixed. 6.syntax bug was fixed to error with Webpack 5.1i. 7.CPU execute real 3MHz(beta1 run 1.5MHz!),and added wait circuit. 8.Adjust pin I/F to UniversalVideoBus. 9 added an alpha version of NTSC video encoder. 10.supported Basaro's Z80IP. Basaro's Z80IP is smaller than Daniel Wallner's T80. Though a special license is necessary for it, You can implement FPGA-PACMAN on XC2S100-tq144,if you have this license 11.support to build without CLUT/PALETTE/SOUND ROM file. (but, color palette and sound tone are incorrect)