//
// FPGA PACMAN clock generator
//
// Version : beta1
//
// Copyright(c) 2002 Tatsuyuki Satoh , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial use. 
// An author does no guarantee about this program.
// You can use this under your own risk. 
//
//

module clock(CLKIN,CLK_2_3,CLK_1_6,CLK_1_6_n);
input  CLKIN;
output CLK_2_3;
output CLK_1_6;
output CLK_1_6_n;

//
// 2/3 clock divider(duty 33%)
//

reg [1:0] clk_pris,clk231,clk232;
//PCLK  1010101010101010101
//pri0  0011110011110011110
//pri1  0011000011000011000
//C231  0000110000110000110
//C232  0110000110000110000
//C2_3  0000110110110110110
always @(posedge CLKIN)
begin
	clk_pris[0] <= ~clk_pris[0]|clk_pris[1];
	clk_pris[1] <= ~clk_pris[0]&~clk_pris[1];
	clk231 = clk_pris[0] & clk_pris[1];
end
always @(negedge CLKIN)
	clk232 = ~clk_pris[0] & ~clk_pris[1];

// 2/3 clock duty 66%
assign CLK_2_3 = clk231|clk232;

//
// 1/3 clock divider (duty 50%)
//
reg CLK_16 , CLK_16n;
always @(posedge CLK_2_3)
begin
	CLK_16n <=  CLK_16;
	CLK_16  <= ~CLK_16;
end
assign CLK_1_6   = CLK_16;
assign CLK_1_6_n = CLK_16n;

endmodule